1. Field of the Invention
The present invention relates to a 3-state bidirectional buffer and a portable semiconductor storage device incorporating the same and, more specifically, an improvement in the electrical characteristics and usability of the portable storage device.
2. Description of the Related Art
FIG. 3 shows the construction of a conventional portable semiconductor storage device. The storage device has a plurality of One Time Programmable Read Only Memory OTPROMs (EPROMs) or Erasable Programmable Read Only Memory 2a to 2h, each OTPROM being connected, via a unidirectional buffer 3, with an address bus 7. Between each of the OTPROMs 2a to 2h and the address bus 7, a CE (chip enable) decoder 4 and a PGM (program) decoder 5 are connected. Each of the OTPROMs 2a to 2h is also connected with a data bus 13.
When a chip enable signal CE is input to the CE decoder 4, a CE selection signal is supplied from the CE decoder 4 to one of the OTPROMs 2a to 2h which has the address specified on the address bus 7. Similarly, when a program signal PGM is input to the PGM decoder 5, a PGM selection signal is supplied from the PGM decoder 5 to one of the OTPROMs 2a to 2h which has the address specified on the address bus 7. Each of the OTPROMs 2a to 2h performs, on the basis of the combination of the levels of the CE selection signal, the PGM selection signal and an OE (output enable) signal input through the unidirectional buffer 3, an operation such as a reading operation or a program operation. For example, during a reading operation, the data stored in the specified address is read from the pertinent OTPROM to the data bus 13.
In such a semiconductor storage device, the input capacitance of a signal to be input to one of the OTPROMs 2a to 2h, and the output capacitance of a signal to be output therefrom are each the sum of the individual input or output capacitance of the OTPROM and the stray capacitance resulting from the circuit wiring. Therefore, the total capacitance Cit of an input signal and the total capacitance Cot of an output signal can be expressed by the following equations if the individual input capacitance of each OTPROM is expressed as Ci, the individual output capacitance of each OTPROM is expressed as Co, and the stray capacitance resulting from the circuit wiring is expressed as Cs: EQU Cit=N.times.Ci+Cs EQU Cot=N.times.Co+Cs
where N represents the number of OTPROMs provided in the storage device. It is assumed here that the signals are subjected to the same stray capacitance.
If N=16, Ci=6 pF, Co=6 pF, and Cs=20 pF, the total input signal capacitance Cit and the total output signal capacitance Cot calculated by the respective equations will both be 116 pF, a considerably large value. The unidirectional buffer 3, the CE decoder 4 and the PGM decoder 5, all incorporated in the semiconductor storage device shown in FIG. 3, serve to reduce the total capacitance of a signal to be input to one of the OTPROMs 2a to 2h.
Let us now examine the magnitude of current that must be applied to drive an input capacitance of 116 pF. A current i is expressed in terms of a capacitance C and a change in voltage within a period .DELTA.V/.DELTA.t, as follows: EQU i=C.multidot..DELTA.V/.DELTA.t
In order to calculate the magnitude of the current, therefore, if it is assumed that C=Cit=Cot=116 pF, and that a rise or drop in voltage through a voltage amplitude .DELTA.V=4 v occurs within a rising or falling period .DELTA.t=10 ns, the current i is expressed as follows: EQU i=116.times.10.sup.-12 .times.4/(10.times.10.sup.-9)=46.4 mA
Thus, it is understood that a considerably large current must be driven.
In order to cope with this fact, if a plurality of semiconductor memories are incorporated in a storage device, as in the case of the storage device shown in FIG. 3, the unidirectional buffer 3, the CE decoder 4 and the PGM decoder 5 must be provided to reduce the input capacitance of the storage device.
Although the capacitance on the input side can be reduced in this way, it is impossible to reduce the capacitance on the side of the data bus 13 because it is difficult to insert a buffer connected to the data bus 13.
The functions of the OTPROMs 2a to 2h will be described. Table-1 shows the functions of OTPROMs comprising, for example, the M5M27C100P (product of Mitsubishi).
TABLE 1 ______________________________________ DATA Vpp Vcc INPUT MODE CE OE PGM (v) (v) OUTPUT ______________________________________ READING L L X 5 5 OUTPUT OUTPUT L H X 5 5 FLOATING DISABLE STAND-BY H X X 5 5 FLOATING (POWER DOWN) WORD L H L 12.5 6 INPUT PROGRAM PROGRAM L L H 12.5 6 OUTPUT VERIFYING PAGE DATA H L H 12.5 6 INPUT LATCHING PAGE H H L 12.5 6 FLOATING PROGRAM PROGRAM L L L 12.5 6 FLOATING INHIBITION L H H 12.5 6 H L L 12.5 6 H H H 12.5 6 ______________________________________
As shown in Table-1, a writing operation (program operation) can be performed in a mode such as the word program mode, the program verifying mode or the page data latching mode. In order to perform such a writing operation, control over both the program voltage Vpp and the program signal PGM is necessary. Hitherto, however, there has been no buffer that is capable of controlling both the program voltage Vpp and the program signal PGM.
FIG. 4 shows a generally known conventional bidirectional buffer. The buffer includes inverters 20f to 20j, and AND circuits 52a and 52b. The inverters 20f and 20h input a direction control signal DIR and an output enable signal OE, respectively. The output lines from the inverters 20i and 20j serve as an input control signal line 41 and an output control signal line 42, respectively. These signal lines 41 and 42 are respectively connected with 3-state non-inverters 25a and 25b, both 3-state non-inverters 25a and 25b forming bidirectional data ports A and B. Although the input control signal line 41 and the output control signal line 42 are connected to similar bidirectional data ports, these other ports are not illustrated in FIG. 4 in order to make the explanation simple.
When the output enable signal OE received by the inverter 20h is at a high ("H") level, since the output of the inverter 20h is at a low ("L") level, the input control signal line 41 and the output control signal line 42 are both brought to an "L" level, whereby the data ports A and B assume their floating condition. When both of the received output enable signal OE and the received direction control signal DIR are at the "L" level, the input control signal line 41 is brought to the "L" level while the output control signal line 42 is brought to the "H" level, whereby the non-inverter 25a assumes its floating condition while the non-inverter 25b assumes its active condition so that transmission is possible from the data port B to the data port A. When the received output enable signal OE is at the "L" level while the direction control signal DIR is at the "H" level, since the input control signal line 41 is brought to the "H" level while the output control signal line 42 is brought to the "L" level, the non-inverter 25a becomes active while the non-inverter 25b becomes floating so that transmission is possible from the data port A to the data port B.
In this way, the conventional buffer operates, in accordance with an output enable signal OE and a direction control signal DIR, to enable either transmission from the data port A to the data port B or transmission from data port B to the data port A. However, the buffer does not have terminals for inputting the program voltage Vpp and the program signal PGM. It will be understood, therefore, that the conventional buffer is not able to cover all the functions shown in Table-1. In addition, the program voltage Vpp, which rises to 12.5 V during program operation, and thus exceeds the absolute maximum rated voltage of a general IC, makes it impossible for such a buffer to exist.
As a result, the data bus 13 connected to the OTPROMs 2a to 2h becomes continuously loaded with a large capacitance, thereby making it difficult to perform accessing at high speed.
As described above, with a conventional portable semiconductor storage device incorporating a plurality of semiconductor memories such as OTPROMs or EPROMs, the input or output capacitance is of such a great value that it has been impossible to obtain high-speed accessing. In addition, since the input and output terminals of the semiconductor memories are directly connected to an external circuit, there is a risk that the semiconductor memories may be broken or deteriorated by external static electricity or the like.